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FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
Integrated Device Technology, Inc.
IDT54/74FCT162H272AT/CT/ET
FEATURES:
* * * * * * * * * * * 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1A (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack Extended commercial range of -40C to +85C Balanced Output Drivers: 24mA (commercial) 16mA (military) Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25C Bus Hold retains last active bus state during 3-state Eliminates the need for external pull up resistors
DESCRIPTION:
The FCT162H272AT/CT/ET synchronous tri-port bus exchangers are high-speed, bidirectional,12-bit, registered, bus
multiplexers for use in synchronous memory interleaving applications. All registers have a common clock and use a clock enable (CExxx) on each data register to control data sequencing. The output enables and mux select (OEA, OEB and SEL) are also under synchronous control allowing direction changes to be edge triggered events. The tri-port bus exchanger has three 12-bit ports. Data may be transferred between the A port and either/both of the B ports. The clock enable (CE1B, CE2B, CEA1B and CEA2B) inputs control the data storage. Both B ports have a common output enable (OEB) to aid in synchronously loading the B registers from the B port. The FCT162H272AT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors. The FCT162H272AT/CT/ET have "Bus Hold" which retains the input's last state whenever the input goes to high impedance. This prevents "floating" inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
CEA1B CLK
CE A-1B REGISTER Q D
12
1B1:12
CE1B SEL OEB OEA A1:12 12 CE2B 12 12 CEA2B M1 U X0 12 CONTROL REGISTER 12
CE 1B-A REGISTER D Q
12
CE 2B-A REGISTER Q D 12
CE A-2B REGISTER Q D
12
2B1:12
3071 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-3071/3
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IDT54/74FCT162H272AT/CT/ET FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN CONFIGURATIONS
CEA1B CEA2B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 OEA SEL
1 2 3 4 5 6 7 8 9 10 11 12 13
56 55 54 53 52 51 50 49 48 47 46 45 44
CE1B CE2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 OEB CLK
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CEA1B CEA2B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 OEA SEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CERPACK TOP VIEW E56-1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CE1B CE2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 OEB CLK
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14 SO56-1 43 SO56-2 15 SO56-3 42 16 17 18 19 20 21 22 23 24 25 26 27 28 41 40 39 38 37 36 35 34 33 32 31 30 29
SSOP/ TSSOP/TVSOP TOP VIEW
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IDT54/74FCT162H272AT/CT/ET FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN DESCRIPTION
Signal A(1:12) 1B(1:12) 2B(1:12) CLK I/O I/O I/O I/O I I I I I I I I Description Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.(1) Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.(1) Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.(1) Clock Input. Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW). Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW). Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW). Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW). 1B or 2B Path Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port. Synchronous Output Enable for A Port (Active LOW). Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
3071 tbl 01
CEA1B
CEA2B CE1B CE2B
SEL
OEA OEB
NOTES: 1. On FCT162H272T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max. VTERM(2) Terminal Voltage with Respect to -0.5 to +7.0 GND -0.5 to VTERM(3) Terminal Voltage with Respect to GND VCC +0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120 Unit V V
FUNCTION TABLES(2)
1B H L X X X X X 2B X X X H L X X Inputs SEL CE1B H H H L L L X L L H X X X X
CE2B OEA
X X X L L H X L L L L L L H
CLK
Output A H L A(1) H L A(1) Z
3071 tbl 04
C
mA
3071 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT.
Inputs A H L
Outputs
CEA1B CEA2B
L L L L H H H X X L L H H L L H X X
OEB
L L L L L L L H L
CLK
1B H L H L B(1) B(1) B(1) Z Active
2B H L B(1) B(1) H L B(1) Z Active
CAPACITANCE (TA = +25C, F = 1.0MHZ)
Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0 pF
3071 tbl 03
H L H L X X X
NOTE: 1. This parameter is measured at characterization but not tested.
3071 tbl 05 NOTES: 1. Output level before the indicated steady-state input conditions were established. 2. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Transition
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IDT54/74FCT162H272AT/CT/ET FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 10%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) II L Input LOW Current(4) IBHH IBHL IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Bus Hold Standard Input(5) Standard I/O(5) Bus-Hold Input Bus-Hold I/O Standard Input(5) Standard I/O(5) Bus-Hold Input Bus-Hold I/O Bus-Hold Input VCC = Min. VI = 2.0V VI = 0.8V VCC = Max. VCC = Min., IIN = -18mA VCC = Max., VO = GND(3)
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC
Min. 2.0 -- -- -- -- --
Typ.(2) -- -- -- -- -- -- -- -- -- -- -- --
-- -- -0.7 -140
Max.
--
Unit V V
0.8
1 1 100 100 1 1 100 100
-- --
A
VI = GND
-- -- -- -- -50 +50 -- -- -- -80 -- --
A
Sustain Current(4) High Impedance Output Current (3-State Output pins) (5,6) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current
VO = 2.7V VO = 0.5V
1 1
-1.2 -225 --
A
V mA mV
100 5
VCC = Max., VIN = GND or VCC
500
A
3071 tbl 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162H272T
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -16mA MIL. IOH = -24mA COM'L. IOL = 16mA MIL. IOL = 24mA COM'L. Min. 60 -60 2.4 -- Typ.(2) 115 -115 3.3 0.3 Max. 200 -200 -- 0.55 Unit mA mA V V
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NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Pins with Bus Hold are identified in the pin description. 5. The test limit for this parameter is 5A at TA = -55C. 6. Does not include Bus Hold I/O pins.
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IDT54/74FCT162H272AT/CT/ET FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open One Output Port Enabled CExx = GND One Input Bit Toggling One Output Bit Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle One Output Port Enabled CExx = GND One Input Bit Toggling One Output Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle One Output Port Enabled CExx = GND Twelve Input Bits Toggling Twelve Output Bits Toggling Min. -- -- Typ.(2) 0.5 60 Max. 1.5 100 Unit
mA A/ MHz
VIN = VCC VIN = GND
IC
Total Power Supply Current (6)
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
0.6
1.5
mA
--
0.9
2.3
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
1.8
3.5 (5)
--
4.8
12.5 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
3071 tbl 09
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IDT54/74FCT162H272AT/CT/ET FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162H272AT Com'l. Symbol Parameter Mil. FCT162H272CT Com'l. Mil. FCT162H272ET Com'l. Mil.
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH tPHL tPLH tPHL
tPZH tPZL tPHZ tPLZ tSU tSU tSU tSU
OEB to CLK
Propagation Delay CLK to 1Bx or CLK to 2Bx Propagation SEL Stable Delay CExB Enabled CLK to Ax SEL Changing CExB Disabled SEL Changing CExB Enabled Output Enable Time CLK to Ax, CLK to 1Bx, or CLK to 2Bx Output Disable Time CLK to Ax, CLK to 1Bx, or CLK to 2Bx Set-Up Time, HIGH or LOW Data to CLK Set-Up Time, OEA to CLK, Set-Up Time, SEL to CLK
CL = 50pF RL = 500
1.5 1.5 1.5 1.5 1.5
5.8 6.0 6.0 7.6 7.7
1.5 1.5 1.5 1.5 1.5
6.2 6.4 6.4 7.9 8.1
1.5 1.5 1.5 1.5 1.5
5.2 5.4 5.4 6.6 6.8
1.5 1.5 1.5 1.5 1.5
5.6 5.8 5.8 7.0 7.2
1.5 1.5 1.5 1.5 1.5
4.8 5.0 5.4 5.6 6.0
-- -- -- -- --
-- -- -- -- --
ns ns ns ns ns
1.5
6.4
1.5
6.8
1.5
6.0
1.5
6.4
1.5
5.6
--
--
ns
2.0 2.0 2.0 2.0
-- -- -- --
2.0 2.0 2.0 2.0
-- -- -- --
2.0 2.0 2.0 2.0
-- -- -- --
2.0 2.0 2.0 2.0
-- -- -- --
2.0 2.0 2.0 2.0
-- -- -- --
-- -- -- --
-- -- -- --
ns ns ns ns
Set-Up Time, CEA1B to CLK, CE1B to CLK, CE2B to CLK, or CEA2B to CLK Hold Time, CLK to Data Hold Time, CLK to OEA, CLK to OEB, CLK to SEL Hold Time, CLK to CEA1B, CLK to CE1B, CLK to CE2B, CLK to CEA2B Pulse Width, CLK HIGH (4) Skew (3)
tH tH tH
0 0.5 0
-- -- --
0 0.5 0
-- -- --
0 0.5 0
-- -- --
0 0.5 0
-- -- --
0 0.5 0
-- -- --
-- -- --
-- -- --
ns ns ns
tW
3.0 --
-- 0.5
3.0 --
-- 0.5
3.0 --
-- 0.5
3.0 --
-- 0.5
3.0 --
-- 0.5
-- --
-- --
ns ns
tSK(o) Output
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested.
3071 tbl 10
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IDT54/74FCT162H272AT/CT/ET FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL
3071 lnk 04
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Open
Switch
Closed
7.0V
V OUT
3032 tbl 11 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
500
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. t REM 3V 1.5V 0V 3V 1.5V 0V
3071 lnk 05
PULSE WIDTH
3V 1.5V 0V 3V 1.5V 0V
tH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
3071 lnk 06
t SU
tH
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL t PLH OPPOSITE PHASE INPUT TRANSITION t PHL 3V 1.5V 0V
3071 lnk 07
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY SWITCH LOW CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V
3071 drw 08
DISABLE 3V 1.5V tPLZ 0V 3.5V VOL
SAME PHASE INPUT TRANSITION t PLH OUTPUT t PHL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT162H272AT/CT/ET FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
ORDERING INFORMATION
IDT FCT X XX Drive Temp. Range X Bus Hold XXXX Device Type X Package X Process
Blank B PV PA PF E 272AT 272CT 272ET H
Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1) 12-Bit Synchronous Tri-Port Bus Exchanger
Bus Hold
162 54 74
16-Bit Balanced Drive -55C to +125C -40C to +85C
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